Memory with vectorial access

ABSTRACT

A parallel memory configured to enable access to a table with aligned and equidistant components constituting a vector of N components. The memory ( 1 ) is organized as M memory banks ( 8 ). Each memory bank ( 8 ) includes an address calculator. The memory ( 1 ) also includes a unidirectional network ( 6 ) configured to carry out a permutation of the N components of the vector being accessed and to carry out a translation by a specified value t of the components of the vector.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The field of the invention is that of parallel memories which constitutean interesting approach for adapting the memory throughput to thecomputational power which can be installed nowadays on an integratedcircuit.

2. Background of the Invention

A parallel memory is a memory which is capable of reading or writingfrom or to several memory slots in a single access cycle. A SingleInstruction Multiple Data (SIMD) is a conventional device that usesparallel memory which can be accessed by all of a device's elementaryprocessors. A SIMD eliminates the need for communication between adevice's elementary processors, thereby greatly simplifying the mannerof operation and appreciably enhancing the performance of device ascompared to a device not equipped with a SIMD.

SIMD machines are mainly used generally to process data organized intables and in particular for signal processing. Since they execute thesame instruction in the same cycle, the elementary processors of an SIMDmachine must access aligned and equidistant data components within asingle table. These data components may constitute a vector, therebyprompting the name “vectorial access memory.” When processing data, itmay be necessary to access vectors with a predetermined orientation withrespect to the axes of the single table, or which are, at the veryleast, parallel to any axis of this table. Likewise, any number ofcomponents of the table can separate two successively consideredcomponents in the vector. These constraints mean that a vectorial accessmemory cannot be constructed simply by juxtaposing blocks of RAM memory,the abbreviation standing for the expression “Random Access Memory”.These constraints make it necessary to choose the number of bankscarefully and to have address calculators which obey particular rules ofinstallation of the tables in memory. Finally, these constraints requirefunctions for reorganizing components of the vector intervening beforewriting or after reading to or from the banks.

R. C. Swanson in his article “Interconnections for parallel memories tounscramble pordered vectors” published under the reference IEEETransactions on computers, vol. C-23, No. 11, November 1974, presents insection II an SIMD calculator model implementing a parallel memory.Swanson shows examples of installing 2D tables in this memory. Swansonalso gives a definition of p-ordered vectors and indicates the advantageof flexibility afforded by a prime number of memory banks. Swanson alsoaddresses a vector reordering problem and proposes networks that make itpossible to reorder a vector. Swanson does not, however, indicate how toproduce a parallel memory. In particular, Swanson does describe howtheaddresses applied to the banks are to be calculated. Swanson also onlydiscloses an installation of tables limited to two dimensions so thatthe proposed network requires that the elements of the reordered vectorundergo an excessively complicated process of multiple routingsdependent on the initial p-ordering thereof.

SUMMARY OF INVENTION

To provide a more efficient and capable memory access device, theinvention proposes an embodiment of a memory with vector access.Accordingly, the subject of the invention is a data memory for dataorganized as tables, whose structure allows accesses via vectors of Ncomponents, and which is addressed according to a specified base of aresidue number system, characterized in that it is organized as M memorybanks of K slots, each bank, numbered between 0 and M−1, comprising anaddress calculator for calculating the local address in the relevantbank of a component i of the vector being accessed and in that itcomprises a unidirectional network carrying out a permutation of thecomponents of the vector being accessed which consists, either in goingfrom an n-ordered vector to a 1-ordered vector, or in going from a1-ordered vector to an n-ordered vector, this network furthermorecarrying out a translation by a specified value t of the components ofthe vector being accessed. A memory according to the invention isstructured as several banks. The management of the memory locations,such as is allowed by the address calculator of each bank associatedwith the network for permuting the components of the vectors, is carriedout in such a way as to optimize accesses to the memory so as toincrease the throughput thereof. The network comprises a number oflayers and a number of modes of operation per layer which are determinedas a function of a compromise between speed and simplicity. Speed is notcompatible with a high number of layers. Simplicity requires arestricted number of modes of operation.

LIST OF FIGURES

Particular characteristics and advantages of the invention will becomeapparent with the aid of the description which follows in conjunctionwith the following drawings:

FIG. 1 describes the general organization of the data paths of a memoryaccording to one embodiment of the invention,

FIG. 2 describes a correspondence between a physical structure and afunctional structure of a memory,

FIG. 3 describes the addressing of the memory banks,

FIG. 4 describes a calculation block of an address calculator,

FIG. 5 describes a first set of layers of a network of a memoryaccording to the invention,

FIG. 6 describes a second set of layers of the network,

FIG. 7 describes a table of correspondence between ordering stride p andmodes-of operation of the layers of the first set of layers, and

FIG. 8 describes a table of correspondence between translation value tand mode of operation of the layers of the second set of layers.

DESCRIPTION OF THE INVENTION

Throughout the document, the terms modulo and 5 mod are entirelyidentical.

FIG. 1 diagrammatically represents the general organization of the datapaths of a memory 1 according to the invention addressed by way of anaddress bus 2 and linked to a calculator 3. The memory 1 comprises astorage block 4, a first switch 5, a network 6 and a second switch 7.The storage block 4 comprises M memory banks 8 labeled from 0 to M−1.The first switch 5 has two input data buses, E1 and E2, and an outputdata bus S1. The first switch 5 links one of the two input data buses,E1 or E2, with the output data bus S1. The network 6 is unidirectional.It is composed of sets of layers. Each layer operates according to aspecified mode of operation determined from among various modes ofoperation. The second switch 7 has an input data bus E3 and two outputdata buses, S2 and S3. The second switch 7 links the input data bus E3with one of the two output data buses, S2 or S3. The calculator 3comprises Q elementary processors 9 labeled from 0 to Q−1, an input databus and an output data bus.

The output data bus of the storage block 4 is connected to the inputdata bus E1 of the first switch 5.

The output data bus S1 of the first switch 5 is connected to the inputdata bus of the network 6.

The output data bus of the network 6 is connected to the input data busE3 of the second switch 7.

The output data bus S2 of the second switch 7 is connected to the inputdata bus of the calculator 3. The output data bus S3 of the secondswitch 7 is connected to the input data bus of the storage block 4.

The output data bus of the calculator 3 is connected to the input databus E2 of the first switch 5.

Physically the memory consists of M banks, each labeled by an index mwith 0≦m<M. Each bank consists of K memory slots, each labeled in itsbank by an index k with 0≦k<K. The physical structure of the memorytherefore corresponds to a 2D table, 2D being the abbreviation for twodimensions, herein referred to as MP, having a “Bank” dimension of sizeM, a “slot” dimension of size K, containing MxK elements; MxK also beingthe total capacity of the memory. An element of this 2D table is labeledby two indices: m,k. Let MP(m,k) be such an element.

Functionally the memory is regarded as a linear space, that is to say a1D table, 1D being the abbreviation for one dimension, referred tohereinbelow as MF of M×K elements, each labeled by an index: @L withOS@L<M×K. Let MF(@L) be such an element.

FIG. 2 illustrates the distribution along the diagonals of the elementsof MF over the elements of MP: MF(0)→MP (0,0), MF(1)→MP(1,1), . . . ,MF(54)→MP (5,6), MF(55)→MP (6,7).

A diagonal is resumed each time it exits on the right, respectively atthe top, in the leftmost column of the table MP but one row higher up,respectively in the lowest row but one column further to the right. If Mand K are relatively prime, it is known to the person skilled in theart:

that MF(M×K−1)→MP(M−1,K−1); in the case of the example adopted andrepresented in FIG. 2 this correspondence corresponds toMF(7×8−1)=MF(55)→MP(7−1,8−1)=MP(6,7), this actually being the case,

that to each element of MP(m,k) there is distributed one and only oneelement of MF: MF(@L) with m=(@L)(modM) and k=(@L)(modK).

Stated otherwise, the indices m and k of the element of MP over whichthe element of MF of index @L is distributed, correspond to theexpression of @L in a residue number system, denoted by the abbreviationRNS, whose base is (M,K). The residue number system, RNS, is a systemknown to the person skilled in the art and in particular from the bookby Szabo and Tanaka “Residue Arithmetic and its Applications to ComputerTechnology”, Mc GRAW-HILL BOOK COMPANY 1967. A number x expressed in RNSaccording to a base (X, Y) equals, the residual value obtained modulo X,the residual value obtained modulo Y. For example 25 equals 4,1 to thebase (7,8), since 25 modulo 7 equals 4 and 25 modulo 8 equals 1.

The memory which corresponds to the illustration of FIG. 2 is addressedin an RNS system with base (7, 8). The maximum number of elements whichcan be addressed is 56, i.e. 7×8. These elements are numbered from 0 to55. During a memory write or read of a vector, it is necessary to knowthe address of the components of the vector.

In a memory according to the invention, each memory bank comprises anaddress calculator 10 as illustrated by FIG. 3.

The memory makes it possible to read or write in a single clock cycle Mcomponents of a vector being accessed. A vector has an origin which islabeled by the indices m(0) and k(0) such that

m(0)=@L(0)(mod M);

and

k(0)=@L(0)(mod K).

The components of the vector are regularly distributed, according toconstant index increments [Δm] (mod M) and [Δk] (mod K)in the memorybanks on account of the distribution as described previously with regardto FIG. 2. [Δm] is the increment in the bank dimension and [Δk] is theincrement in the slot dimension. Consider a component i of the vector tobe read or written, it is labeled in memory by the indices m(i) and k(i)such that:

m(i)=[m(0)+i×[Δm](modM)](modM);  (1)

and

k(i)=[k(0)+i×[Δk](modK)](modK)  (2)

where m(i) corresponds to the number of the bank in which component i ofthe vector is located and k(i) corresponds to the number of the slot ofthe bank m(i) in which this component i is located.

During memory access, each bank receives as parameters the values:

[m(0)](modm), k(0), Δk and [Δm]⁻¹(modM) with:

[m(0)](modM) the additive inverse of m(0) modulo M satisfying therelation m(0)+[−m(0)]=0(modM);

[Δm]⁻¹(modM)the inverse of Am modulo M satisfying the relationΔm×[Δm]⁻¹=1(modM).

The address calculator of bank m determines the value i of the componentwhich it contains by extracting i from relation (1):

i=[[m(i)+−[m(0)](modM)](modM)×[(Δm)]⁻¹(modM)I(modM)  (3)

The address calculator 10 comprises a first adder 11 and a firstmultiplier 12. The first adder 11 adds together the number m(i) of thebank of the component i of the vector and the additive inverse, moduloM, of the number m(0) of the bank of the origin of the vector. Thenumber m(i) of the bank of the component i has a value m, the number m(0) of the bank of the origin has a value 0. The result of the additionis multiplied by the first multiplier 12 with the inverse, modulo M, ofthe increment in the bank dimension (Am). The result of themultiplication gives the value i of the component of the vectorcontained in bank m.

Knowing i, and knowing the parameter Δk which the bank receives from ablock outside the memory, for example a compiler, the address calculatorcalculates product i×Δk (modK) with the aid of a calculation block 13.An exemplary embodiment of a calculation block 13 is represented in FIG.4. It does not include any multipliers. Three calculation blocks 15, 16and 17 carry out the multiplications by 2, 4 or 8 without multipliers byleftward shifting by one, two or three bits. Next, three adders 18, 19and 22 carry out all the multiplications from 0 to 15; themultiplication by 16 being achieved separately by a test 23 of i on themost significant bit followed by a leftward shift by 4 bits. Thechoosing of the correct value is done by three multiplexers 20, 21, 25controlled by the value of i.

The data exchanged between the memory and the calculator are structuredin the form of vectors of N components.

The vectors stored in the M memory banks are ordered according to anorder n and are said to be n-ordered.

A vector is said to be n-ordered or of order n when its N components areregularly spaced by a value equal to n. For example, for a 3-orderedvector of 8 components, the components of the vector are held in thefollowing order: 0,3,6,1,4,7,2,5; each component being identified by itsnumber which varies from 0 to 7. The origin 0 of the vector is held in abank which is not necessarily bank 0. The set of components of thevector can be afforded a shift d. Under these conditions the origin 0 ofthe vector is stored in bank d. Going back to the previous example andconsidering the shift d=2, the components of the vector are stored inthe storage block in the following order: 2,5,0,3,6,1,4,7.

The vectors processed by the calculator are 1-ordered, the component iof a vector is processed by the elementary processor i. In particular,the origin 0 of the vector is processed by elementary processor 0.

When the calculator makes a read access to the memory the first switchlinks the input data bus E1 with the output data bus S1 and the secondswitch links the input data bus E3 with the output data bus S2.

When the calculator makes a write access to the memory, the first switchlinks the input data bus E2 with the output data bus S1 and the secondswitch links the input data bus E3 with the output data bus S3.

During a read access to the memory, the vector at the input of thenetwork is n-ordered with its components shifted by a value d, and thevector at the output of the network is 1-ordered and exhibits no shift.

During a write access to the memory, the vector of the input of thenetwork is 1-ordered and exhibits no shift and the vector at the outputof the network is n-ordered and its components are shifted by a value d.

To carry out the permutation and translation of the components of thevector, the unidirectional network is structured as two sets of layers.A first set of layers carries out the permutation of the components ofthe vector so as to transform the n-ordered vector into a 1-orderedvector or conversely so as to transform the 1-ordered vector into ann-ordered vector. Each layer comprises several modes of operation. Thevalue p, defined as the ordering stride, determines the mode ofoperation to be used per layer. A second set of layers carries out thetranslation of the components of the vector so as to align the origin ofthe vector on the elementary processor 0 in the case of a memory read orso as to shift the origin of the vector in the case of a memory write.Each layer comprises several modes of operation. The value t, defined asthe translation value, determines the mode of operation to be used perlayer.

FIGS. 5, 6, 7 and 8 describe exemplary embodiments of the network. FIG.5 diagrammatically shows the first set of layers. FIG. 6diagrammatically shows the second set of layers. FIG. 7 indicates themodes of operation to be used as a function of the ordering stride p.FIG. 8 indicates the modes of operation to be used as a function of thetranslation value t.

The embodiment of the network illustrated by FIGS. 5 and 6 includes afirst set of layers 26 composed of two layers 27 and 28 and a second setof layers 29 composed of two layers 30 and 31. The first layer 27 of thefirst set of layers 26 exhibits five different modes of operation,denoted a, b, c, d and e. The second layer 28 of the first set of layers26 exhibits five different modes of operation, denoted A, B, C, D and E.The first layer 30 and the second layer 31 of the second set of layers29 also exhibit five modes of operation denoted a, b, c, d, e and A, B,C, D, E respectively.

The first table, FIG. 7, makes it possible to determine the mode ofoperation of each of the two layers of the first set. The second table,FIG. 8, makes it possible to determine the mode of operation of each ofthe two layers of the second set.

The operation of the network is illustrated hereinbelow by taking asexample, firstly a memory write of an initially 1-ordered vector storedin the form of a 3-ordered vector with a shift of 7, and subsequently amemory read of a 3-ordered vector shifted by 7.

In the case of the memory write, the determination of the ordering valuep and translation value t is immediate. The vector stored must be3-ordered, consequently p=3. The components of the stored vector must beshifted by 7, consequently t=7. The 30 values of p and t are givendirectly by the order and the shift of the vector.

The ordering value p and translation value t make it possible todetermine the modes of operation of the layers of the network.

The table of FIG. 7 makes it possible to determine for the first set themode of operation of the first layer, mode p1=b, and the mode ofoperation of the second layer, mode p2=D, given that p=3.

On input to the network the vector is 1-ordered and its components arenot shifted. The components of a vector are input to the first layer inthe following order:

0,1,2,3,4,5,6,7,8, . . . 22.

On crossing the first layer, the components of the vector are permuted.The mode of operation of the first layer is determined by the letter bwhich corresponds to the mode p1 selected. The manner of operation isdetailed hereinbelow with regard to FIG. 5.

The first component 0 undergoes no permutation. Indeed, on the verticalline which starts from 0, in the grid of the first layer, no mode letterappears. The second component 1 undergoes a permutation. Indeed, thevertical line which starts from 1 contains the letter b whichcorresponds to the mode p1 adopted. The letter b determines thehorizontal line on which the second component exits, in this case line5. The third component 2 exits on the horizontal line 10 determined bythe letter b positioned on the vertical line which starts from the inputof the third component. And so on and so forth, until the twenty-thirdcomponent 22 which exits on the horizontal line 18.

On exit from the first layer, the components of the vector are in thefollowing order:

0, 14, 5, 19, 10, 1, 15, 6, 20, 11, 2, 16, 7, 21, 12, 3, 17, 8, 22, 13,4, 18, 9.

On entry to the second layer, the components of the vector are in thesame order as they are on exit from the first layer, that is to say:

0, 14, 5, 19, 10, 1, 15, 6, 20, 11, 2, 16, 7, 21, 12, 3, 17, 8, 22, 13,4, 18, 9.

The second layer carries out a permutation of the vector componentspresent on its inputs according to an operation similar to that of thefirst layer. The mode of operation is specific to the layer and isdetermined in the example adopted by the letter D which corresponds tothe mode p2 selected. The operation is detailed hereinbelow with regardto FIG. 5.

The first component 0 undergoes no permutation. Indeed, on thehorizontal line which starts from 0, in the grid of the second layer, nomode letter appears. The second component 14 undergoes a permutation.Indeed, the horizontal line which starts from 1 contains the letter Dwhich corresponds to the mode p2 adopted. The letter D determines thevertical line on which the second component exits, in this case line 19.The third component 5 exits on the vertical line 15 determined by theletter D positioned on the horizontal line which starts from the inputof the third component. And so on and so forth, until the twenty-thirdcomponent 9 which exits on the vertical line 4.

Thus, on exit from the second layer, the components of the vector are inthe following order:

0, 8, 16, 1, 9, 17, 2, 10, 18, 3, 11, 19, 4, 12, 20, 5, 13, 21, 6, 14,22, 7, 15.

After permutation of its components by the first set of layers, thevector has its components shifted by the second set of layers. The tableof FIG. 8 makes it possible to determine for the second set of layersthe mode of operation of the first layer, mode t1=c, and the mode ofoperation of the second layer, mode t2=B, given that t=7.

On entry to the first layer of the second set of layers of the network,the vector of the example has its components 3-ordered. The componentsof the vector are thus in the following order:

0, 8, 16, 1, 9, 17, 2, 10, 18, 3, 11, 19, 4, 12, 20, 5, 13, 21, 6, 14,22, 7, 15.

FIG. 6 makes it possible to determine the order of the components of thevector on exit from the first layer of the second set of layers, then onexit from the network which corresponds to the output of the secondlayer of the second set of layers.

The first layer operates according to the mode t1 equal to c. Theoperation is detailed hereinbelow with regard to FIG. 6.

The first component 0 undergoes a shift 2. Indeed, the vertical linewhich starts from 0, in the grid of the first layer, contains the letterc which corresponds to the mode d1 adopted. The letter c determines thehorizontal line on which the first component 0 exits in this case line2. The second component 8 undergoes the same shift as the firstcomponent 0. Indeed, the grid of the first layer exhibits each mode d1,in the example adopted c, along a diagonal. And so on and so forth untilthe diagonal, which contains the letter of the mode d1, exits the grid.For the next component, in the example the twenty-second component, thediagonal starts again from the intersection between the vertical linesituated below this last component and the horizontal line correspondingto the output 0 of the first layer. The twenty-second component 7 thusexits on the line 0. And so on and so forth until the twenty-thirdcomponent 15 which exits on the horizontal line 1.

On exit from the first layer the components of the vector are in thefollowing order:

7, 15, 0, 8, 16, 1, 9, 17, 2, 10, 18, 3, 11, 19, 4, 12, 20, 5, 13, 21,6, 14, 22.

On entry to the second layer, the components of the vector are in thesame order as they are on exit from the first layer. That is to say:

7, 15, 0, 8, 16, 1, 9, 17, 2, 10, 18, 3, 11, 19, 4, 12, 20, 5, 13, 21,6, 14, 22.

The second layer carries out a translation of the vector componentspresent on its inputs according to an operation similar to that of thefirst layer. The mode of operation is specific to the layer and isdetermined in the example adopted by the letter B which corresponds tothe mode t2 selected. The operation is detailed hereinbelow with regardto FIG. 6.

The first component 7 undergoes a shift of 5. Indeed, the horizontalline which starts from 0, in the grid of the second layer, contains theletter B which corresponds to the mode t2 adopted. The letter Bdetermines the vertical line on which the first component 7 exits inthis case line 5. The second component 15 undergoes the same shift asthe first component. Indeed, the grid of the second layer exhibits eachmode t2, in the example adopted B, along a diagonal. And so on and soforth until the diagonal, which contains the letter of the grid the modet2, exits the grid. When the diagonal exits the grid via a horizontalline, it is then continued by starting from the point of intersectionbetween the vertical line, the first line to the right of the letter ofthe mode t2 furthest to the right, and the horizontal line correspondingto the input 0. When the diagonal exits the grid via a vertical line, itis then continued by starting from the point of intersection between thehorizontal line, the first line above the letter of the mode t2 furthestto the right, and the vertical line corresponding to the output 0. Inthe example adopted the diagonal which contains the mode t2=B exits thegrid on a vertical line. The eighteenth component 5 exits on the line22. The diagonal starts again at the intersection between the horizontalline 18, the first line above the horizontal line corresponding to theeighteenth component, and the vertical line corresponding to the output0. The nineteenth component 13 thus exits on the line 0. And so on andso forth until the twenty-third component 22 which exits on the verticalline 4. Thus, on exit from the second layer, the components of thevector are in the following order:

13, 21, 6, 14, 22, 7, 15, 0, 8, 16, 1, 9, 17, 2, 10, 18, 3, 11, 19, 4,12, 20, 5.

Table 1 of appendix 1 groups together the various forms taken by theprevious vector in the course of the layers of the network. The outputof the second layer of the second set of layers corresponds to theoutput of the network. It is easy to note that the origin 0 of thevector is actually shifted by a value 7 and that the components of thevector are actually 3-ordered; component 1 being at the location 7+3=10,component 2 at the location 10+3=13 and so on modulo 23. Component 6 isthus at the location [7+3×6j (mod23)=2.

Subsequently, the example envisaged corresponds to a memory read of avector whose components are 3-ordered and whose origin is stored in thememory bank 7.

In the case of the memory read, the determination of the ordering valuep and translation value t is not immediate.

The ordering value p is obtained by calculating the inverse, modulo thenumber N of components of the vector, of the order of the vector read.

p=orders⁻¹(modN)  (4)

In the case of the example, relation (4) gives:

p=3⁻¹(mod23)=8 indeed 3×8=24=1(mod23). The translation value t isobtained by solving the following equation:

location (0)+order×t=0(modN) with:  (5)

location (0), the value of the location which corresponds to the bankNo. where the origin of the vector read is located,

order, the value according to which the components of the vector readare ordered. Solving equation (5) in the case of the example gives:

t=13 indeed 7+3×13=46=2×23=0(mod23).

The use of the network is entirely identical whether dealing with awriting of an initially 1-ordered vector whose origin is aligned on theelementary processor 0 and which is to be stored in the form of ann-ordered vector whose origin is to be aligned on a bank m or whetherdealing with a reading of an initially n-ordered vector whose origin isstored in a bank m and which is to be processed by the elementaryprocessors in the form of a 1-ordered vector whose origin is aligned onthe elementary processor 0. The difference between writing and readinglies in the various modes of operation of the layers of the network.

Thus, returning to the example which firstly corresponds to a memorywrite, the modes of operation of the layers of the network are: modep1=b, mode p2=D, mode t1=c, mode t2=B, and which subsequentlycorresponds to a memory read, the various modes of operation of thelayers of the network are: mode p1=b, mode p2=B, mode t1=d and modet2=C. These latter modes of operation are determined by virtue of thetable of FIG. 7 given that p=8, and by virtue of the table of FIG. 8given that t=13.

By utilizing FIGS. 5 and 6, knowing the modes of operation of thevarious layers of the network, it is possible to determine the variousforms taken by the vector on exit from the various layers. The variousforms of the vector of the example are grouped together in table 2 inappendix 2.

The output of the second layer of the second set of layers correspondsto the output of the network. It is easy to note that the origin 0 ofthe vector is at the location 0 and that the components of the vectorare 1-ordered.

Another example is given hereinbelow so as to supplement theillustration given in the case of a memory read. The vector read inmemory is 4-ordered and has an origin stored at location 7.

Relation (4) makes it possible to determine the ordering value p:

p=4⁻¹(mod23) i.e. p=6 since 4×6=24=1(mod23)

Relation (5) makes it possible to determine the value t of the shift:

7+4×t=0(mod23) i.e. t=4 since 7+4×4=23=0(mod23)

The table of FIG. 7 makes it possible to determine the modes ofoperation of the first set of layers: mode p1=d and mode p2=D given thatp=6.

The table of FIG. 8 makes it possible to determine the modes ofoperation of the second set of layers: mode t1=e and mode t2=A giventhat t=4.

By utilizing FIGS. 5 and 6, knowing the modes of operation of thevarious layers of the network, it is possible to determine the variousforms taken by the vector on exit from the various layers. The variousforms of the vector of the example are grouped together in table 3 inappendix 3. The output of the second layer of the second set of layerscorresponds to the output of the network. It is easy to note that theorigin 0 of the vector is at the location 0 and that the components ofthe vector are 1-ordered.

What is claimed is:
 1. A data memory configured to store data organizedas tables, comprising: M memory banks of K slots, the M memory banksnumbered between 0 and M−1, addressed according to a specified base of aresidue number system, and configured to allow access via equidistantvectors of N components, each of the M memory banks comprising anaddress calculator configured to calculate a local address of acomponent of a vector being accessed; and a unidirectional networkconfigured to carry out a permutation of the components of the vectorbeing accessed, said permutation comprising one of a permutation ofgoing from an n-ordered vector to a 1-ordered vector and a permutationof going from a 1-ordered vector to an n-ordered vector, saidunidirectional network configured to carry out a translation, by aspecified value t, of the components of the vector being accessed. 2.The data memory as claimed in claim 1, wherein in order to calculate ina specified memory bank the local address of the component of a vectorwhose origin is stored in a memory bank numbered m(0), the addresscalculator of the specified memory bank comprises: a calculatorconfigured to successively determine a value i of the component of thevector contained in the specified memory bank by means of the followingrelation i=[[m(i)+[m(0)](modM)](modM)×[(Δm)]⁻¹(modM)](modM), wherein−[m(0)](modM), the additive inverse of m(0) modulo M, satisfies therelation m(0)+[−m(0)]=0(modM), [(Δm)]⁻¹(modM)], the inverse of Δm moduloM, satisfies the relation Δm×[(Δm)]⁻¹=1(modM), Δm being the indexincrement with which the components of the vector are stored in thememory banks, the calculation of the local address satisfies therelationship k(i)=[k(0)+i×[Δk](modK)](modK), and ≢k being the indexincrement with which the components of the vector are stored in thememory slots and with k(0) being the number of the memory slot in whichthe origin of the vector is held.
 3. The data memory as claimed in claim1, wherein the unidirectional network comprises: a first set of layers;and a second set of layers, said second set of layers arranged in serieswith the first set of two layers, wherein the first set of layers isorganized to modify, by a value p, the spacing between successivecomponents of a vector present at the input of the network so as toperform at least one of p-ordering of the 1-ordered components of thevector during a memory write and a 1-ordering of the p-orderedcomponents of the vector during a memory read, and the second set oflayers is organized to translate, by a value t, the successivecomponents of the vector modified by the first set of layers saidtranslation so as to perform at least one of a realignment of the originof the vector during a memory read and a shift of the origin of thevector during a memory write.
 4. The data memory as claimed in claim 1,further comprising: a first switch comprising two inputs and an output;and a second switch comprising an input and two outputs, wherein thefirst and second switches are arranged so that the first switch connectsthe output of the M memory banks with the input of the unidirectionalnetwork and the second switch connects the output of the unidirectionalnetwork with the output of the M memory banks during a read access ofthe memory, and the first switch connects the input of the M memorybanks with the input of the unidirectional network, and the secondswitch connects the output of the unidirectional network with the inputof the M memory banks during a write access to the memory.
 5. The datamemory as claimed in claim 2, wherein the spacing value p, thetranslation value t, the index increment Δm, the index increment Δk, thenumber m(0), and the number k(0) each comprise: data supplied to thememory during each read access and write access to the memory.
 6. Thedata memory as claimed in claim 3, wherein the spacing value p, thetranslation value t, the index increment Δm, the index increment Δk, thenumber m(0) and the number k(0) each comprise: data supplied to thememory during each read access and write access to the memory.
 7. Thedata memory as claimed in claim 3, wherein the first set of layers andthe second set of layers respectively comprise: a first set of layersconfigured to operate according to one of a plurality of specified modesof operation determined by the spacing value p; and a second set oflayers configured to operate according to one of a plurality ofspecified modes of operation determined by the translation value t. 8.The data memory as claimed in claim 5, wherein the first set of layersand the second set of layers respectively comprise: a first set oflayers configured to operate according to one of a plurality ofspecified modes of operation determined by the spacing value p; and asecond set of layers configured to operate according to one of aplurality of specified modes of operation determined by the translationvalue t.
 9. The data memory as claimed in claim 3, wherein each of thefirst and second set of layers comprises: a predetermined number oflayers, and a predetermined number of modes of operation, wherein saidpredetermined number of layers and said predetermined number of modesare parameterizable.
 10. The data memory as claimed in claim 5, whereineach of the first and second set of layers comprises: a predeterminednumber of layers, and a predetermined number of modes of operation,wherein said predetermined number of layers and said predeterminednumber of modes are parameterizable.
 11. The data memory as claimed inclaim 7, wherein each of the first and second set of layers comprises: apredetermined number of layers, and a predetermined number of modes ofoperation, wherein said predetermined number of layers and saidpredetermined number of modes are parameterizable.
 12. The data memoryas claimed in claim 9, wherein each of the first set of layers and thesecond set of layers comprise: a first and second layer, said firstlayer configured to correspond to a first set of five modes of operationand said second layer configured to correspond to a second set of fivelayers.
 13. The data memory as claimed in claim 10, wherein each of thefirst set of layers and the second set of layers comprise: a first andsecond layer, said first layer configured to correspond to a first setof five modes of operation and said second layer configured tocorrespond to a second set of five layers.
 14. The data memory asclaimed in claim 11, wherein each of the first set of layers and thesecond set of layers comprise: a first and second layer, said firstlayer configured to correspond to a first set of five modes of operationand said second layer configured to correspond to a second set of fivelayers.